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AD9628

Data Sheet

Rev. C | Page 28 of 42

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 50 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

–1

–2

–3

–4

–5

–6

–40

–20

TEMPERATURE (°C)

VREF ERROR (mV)

Figure 50. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 41). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9628 sample clock

inputs, CLK+ and CLK−, with a differential signal. The signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally

(see Figure 51) and require no external bias.

0.9V

AVDD

2pF

CLK–

CLK+

Figure 51. Equivalent Clock Input Circuit

Clock Input Options

The AD9628 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of the most concern, as described in the Jitter Considerations

section.

Figure 52 and Figure 53 show two preferred methods for clock-

ing the AD9628 (at clock rates up to 1 GHz prior to internal CLK

divider). A low jitter clock source is converted from a single-

ended signal to a differential signal using either an RF

transformer or an RF balun.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 1 GHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

antiparallel Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9628 to

approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9628 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1µF

1nF

CLOCK

INPUT

1nF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 53. Balun-Coupled Differential Clock (Up to 1 GHz)

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