AD9266

Data Sheet

Rev. B | Page 6 of 32

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, DCS disabled, unless otherwise noted.

Table 3.

Parameter

Temp

AD9266-20/AD9266-40/AD9266-65/AD9266-80

Unit

Min

Typ

Max

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.2

3.6

V p-p

Input Voltage Range

Full

GND − 0.3

AVDD + 0.2

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

8

10

12

kΩ

Input Capacitance

Full

4

pF

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−50

−75

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

30

kΩ

Input Capacitance

Full

2

pF

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

40

135

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

Full

3.29

V

Full

3.25

V

Full

0.2

V

Full

0.05

V

DRVDD = 1.8 V

Full

1.79

V

Full

1.75

V

Full

0.2

V

Full

0.05

V

1

Internal 30 kΩ pull-down.

2

Internal 30 kΩ pull-up.