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Data Sheet

AD9266

Rev. B | Page 21 of 32

Input Clock Divider

The AD9266 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

Optimum performance can be obtained by enabling the internal

duty cycle stabilizer (DCS) when using divide ratios other than

1, 2, or 4.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9266 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9266. Noise and distortion perform-

ance are nearly flat for a wide range of duty cycles with the DCS on,

as shown in Figure 51.

POSITIVE DUTY CYCLE (%)

DCS OFF

DCS ON

Figure 51. SNR vs. DCS On/Off

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 µs to 5 µs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR from the low frequency

SNR (SNRLF) at a given input frequency (fINPUT) due to jitter

(tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10

)

(

SNR

−

]

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 52.

100

FREQUENCY (MHz)

0.5ps

0.2ps

0.05ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

Figure 52. SNR vs. Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter may

affect the dynamic range of the AD9266. To avoid modulating the

clock signal with digital noise, keep power supplies for clock

drivers separate from the ADC output driver supplies. Low jitter,

crystal-controlled oscillators make the best clock sources. If the

clock is generated from another type of source (by gating, dividing,

or another method), it should be retimed by the original clock at

the last step.

For more information, see the AN-501 Application Note and

the AN-756 Application Note.

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