AD9255 datasheet(12/45 Pages) AD

12 / 45 page

Data Sheet

AD9255

Rev. C | Page 11 of 44

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SYNC

CLK+

CLK–

AVDD

OEB

DNC

DCO

DNC

D0 (LSB)

DITHER

AVDD

SVDD

CSB

SCLK/DFS

SDIO/DCS

DRVDD

DNC

D13 (MSB)

D12

AVDD

AD9255

PARALLEL

CMOS

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE INPUT. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 4. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

13, 20, 29

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

4, 5, 34, 36, 45

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

SVDD

Supply

SPI Input/Output Voltage

7, 9, 10, 28, 39, 40

DNC

Do Not Connect.

AGND

Ground

Analog Ground. The exposed thermal pad on the bottom of the package provides

the analog ground for the input. This exposed pad must be connected to ground for

proper operation.

ADC Analog

VIN+

Input

Differential Analog Input Pin (+).

VIN−

Input

Differential Analog Input Pin (−).

VREF

Input/output

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select. See Table 11 for details.

RBIAS

Input/output

External Reference Bias Resistor.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

D0 (LSB)

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

Output

CMOS Output Data.

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