LED171596ARSLR datasheet(148/153 Pages) TI1

148 / 153 page

VIN

GND

VDD

VDDIO

Short wide paths on high di/dt node (GND, VLED).

Keep current loops as short as possible.

CVLED

Connect all GND pins to

Thermal Pad and system

ground (GND plane).

TOP Layer GND plane connecting GND to CVLED.

Connect to VLED rail and system ground using

multiple vias to reduce via inductance and

resistance.

148

LED171596A

SNVSAY2 – OCTOBER 2017

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10 Layout

10.1 Layout Guidelines

See Figure 310 for the recommended layout of the LED171596A, which is designed for common system ground

connections. Therefore, connect GND and LGND pins to the exposed thermal pad and the system ground. The

GND plane connections to CVLED and GND pins must be on TOP layer copper with multiple vias connecting to

system ground plane keeping traces as short as wide as possible.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current (VLED, HS3, HS2, HS1 and HS0) must be as short and wide as possible. Parallel wiring over long

distances, as well as narrow traces, must be avoided. Loops that conduct an alternating current must outline an

area as small as possible, as this area is proportional to the energy radiated.

The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve

appropriate power dissipation.

10.2 Layout Example

Figure 310. Layout Example

LED171596ARSLR Datasheet(PDF) 148 Page - Texas Instruments