TUSB564 datasheet(23/45 Pages) TI1

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TUSB564

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SLLSF29A – OCTOBER 2017 – REVISED OCTOBER 2017

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8.5 Programming

For further programmability, the TUSB564 can be controlled using I2C. The SCL and SDA pins are used for I2C

clock and I2C data respectively.

Table 9. TUSB564 I2C Target Address

DPEQ0/A1

PIN LEVEL

SSEQ0/A0

PIN LEVEL

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

0/1

The following procedure should be followed to write to TUSB564 I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB564 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB564 acknowledges the address cycle.

3. The master presents the sub-address (I2C register within TUSB564) to be written, consisting of one byte of

data, MSB-first.

4. The TUSB564 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I2C register.

6. The TUSB564 acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TUSB564.

8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TUSB564 I2C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB564 7-bit

address and a one-value “W/R” bit to indicate a read cycle.

2. The TUSB564 acknowledges the address cycle.

3. The TUSB564 transmit the contents of the memory registers MSB-first starting at register 00h or last read

sub-address+1. If a write to the I2C register occurred prior to the read, then the TUSB564 shall start at the

sub-address specified in the write.

4. The TUSB564 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I2C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the TUSB564 transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB564 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB564 acknowledges the address cycle.

3. The master presents the sub-address (I2C register within TUSB564) to be written, consisting of one byte of

data, MSB-first.

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