VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC838

3.2Gb/s

36x37 Crosspoint Switch

Page 4

G52351-0, Rev 3.0

02/12/01

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Serial Read-Back

Read-back of the program memory contents is accomplished in serial mode by setting the ALE_SCN pin

HIGH. This will serially shift out the contents of the main latches in the program memories, slice 36 first and

slice 0 last, and MSB-first, LSB-last for each 7-bit word (see Figure 3). One rising edge of INCHAN[1](SCLK)

with ALE_SCN=0 and SERIAL=1 must occur to load the entire 483-bit shift register prior to shifting out data.

At a clock rate of 66MHz, this operation takes 7.26

µs.

Activity Monitoring

edge of ACTCLK causes the monitor to read out the activity state from the previous ACTCLK period and clears

the internal activity state until a data transition triggers it again. There must be a minimum of one rising and one

falling edge on the observed input data pin during the ACTCLK period for activity to be detected. After power-

on the output of ACTIVITY after the first ACTCLK rising edge is unknown.

Selective Power-Down

Unused input and output channels can be made to consume little or no power via one of two methods of

selective power-down.

Software Power-Down

Using this feature, unused outputs may be disabled, saving approximately 170 mW per channel for maxi-

mum dissipation conditions. This is accomplished by programming each unused output to look at input 127 (7F

Hex), which represents a non-existent input channel. The channel may be subsequently activated by program-

ming a valid input address. It is recommended, however, that any changes in power programming only be exe-

cuted as part of an initialization sequence to guard against the effects of any switching transients that might

result from changing the power supply current suddenly. Software mode does not affect the functioning or

power of unused input channels.

Hardware Power-Down

Using this feature, the power associated with given pairs of inputs may be shut off by tying the correspond-

tion conditions. The power associated with given pairs of outputs, including their contribution to the core

output pair is saved under the maximum dissipation conditions.

ing inputs and outputs will always be on and consuming power. See Figure 7 and Table 10 for the location of

these pins.