VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC838

3.2Gb/s

36x37 Crosspoint Switch

G52351-0, Rev 3.0

Page 1

02/12/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Features

General Description

The VSC838 is a monolithic 36x36 asynchronous crosspoint switch, designed to carry broadband data

Monitor to allow in system diagnostics.

A high degree of signal integrity is maintained throughout the chip via fully differential signal paths.

The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 36:1

multiplexer that can be programmed to one and only one of its 36 inputs. The signal path is unregistered and

fully asynchronous, so there are not any restrictions on the phase, frequency, or signal pattern at each input.

Each high-speed output is a fully differential, switched current driver with switchable on-die terminations

for maximum signal integrity. Data inputs are terminated on-die through 100

Ω impedance between true and

complement inputs (see Input Termination section for further details).

A dual mode programming interface is provided that allows programming commands to be sent as serial

data or parallel data. Core programming can be random for each port address, or multiple program assignments

can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configu-

ration (A0 to Y0, A1 to Y1, etc.) using the INIT pin.

Unused channels may be powered down to allow efficient use of the switch in applications that require only

a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of

input and output channels, or in software by programming individual unused outputs with a disable code.

VSC838 Block Diagram

• 36 Input by 37 Output Crosspoint Switch

• 3.2Gb/s NRZ Data Bandwidth

• Non-Blocking Architecture Broadcast and Multicast

Capabilities

• LVTTL/2.5V CMOS Control I/O (3.3V tolerant)

• Input Signal Activity Monitoring Function

• Integrated Signal Equalization (ISE) for Deterministic

Jitter Reduction

• 66MHz Dual Programming Port

• Parallel and Serial programming modes

• Programmable On-Chip I/O Termination

• Differential CML Output Drivers

• Single 2.5V Supply

• 6W Typical—Low Drive Mode

7W Typical—High Drive Mode

• High Performance 37.5mm, 480 TBGA Package

2

2

2

2

A0

A35

Y0

Y35

µP

control