AD5252EVAL datasheet(14/28 Pages) AD

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AD5251/AD5252

Rev. 0 | Page 14 of 28

SIGN

7 BITS FOR INTEGER NUMBER

8 BITS FOR DECIMAL NUMBER

2–8

2–1

2–2

2–3

2–4

2–5

2–6

2–7

Figure 12. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)

RAB Tolerance Stored in Read-Only Memory

The AD5251/AD5252 feature patented RAB tolerances storage in

the nonvolatile memory. The tolerance of each channel is stored

in the memory during the factory production and can be read

by users at any time. The knowledge of stored tolerance, which

is the average of RAB over all codes (see Figure 28), allows users

to predict RAB accurately. This feature is valuable for precision,

rheostat mode, and open-loop applications where knowledge of

absolute resistance is critical.

The stored tolerances reside in the read-only memory, and are

expressed as a percentage. The tolerance is stored in two

memory locations (see Table 10). The data format of the

tolerance is in sign magnitude binary form. An example is

shown in Figure 11. In the first memory location, the MSB is

designated for the sign (0 = + and 1= –) and the 7 LSBs are

designated for the integer portion of the tolerance. In the

second memory location, all eight data bits are designated for

the decimal portion of tolerance. As shown in Table 10 and

Figure 12 for example, if the rated RAB = 10 kΩ and the data

readback from Address 11000 shows 0001 1100 and Address

11001 shows 0000 1111, then RDAC0 tolerance can be

calculated as

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

8 LSB: 0000 1111 = 15 × 2–8 = 0.06

Tolerance = +28.06% and therefore

RAB_ACTUAL = 12.806 kΩ

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal

write cycle begins. The I2C interface of the device is disabled. To

determine if the internal write cycle is complete and the I2C

interface is enabled, interface polling can be executed. I2C

interface polling can be conducted by sending a start condition

followed by the slave address + the write bit. If the I2C interface

responds with an ACK, the write cycle is complete and the

interface is ready to proceed with further operations. Other-

wise, I2C interface polling can be repeated until it succeeds.

Commands 2 and 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to a logic LOW after EEMEM programming

protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read

operations operate as normal. When write protection is

enabled, Command 1 (Restore from EEMEM to RDAC) and

Command 7 (Reset) function normally to allow RDAC settings

to be refreshed from the EEMEM to the RDAC registers.

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