TMSC6701 datasheet(4/64 Pages) TI

4 / 64 page

TMS320C6701

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS067E – MAY 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

functional block and CPU diagram

Control

Logic

Test

’C67x CPU

Data Path B

B Register File

Program

Access/Cache

Controller

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

Data

Access

Controller

Power-

Down

Logic

.L1† .S1† .M1† .D1

.D2 .M2† .S2† .L2†

ROM/FLASH

SRAM

I/O Devices

Timer 0

Timer 1

External Memory

Interface (EMIF)

Multichannel

Buffered Serial

Port 0

Multichannel

Buffered Serial

Port 1

Direct Memory

Access Controller

(DMA)

(4 Channels)

Host Port

Interface

(HPI)

Internal Program Memory

1 Block Program/Cache

(64K Bytes)

Control

Registers

Internal Data

Memory

(64K Bytes)

2 Blocks of 8 Banks

Each

In-Circuit

Emulation

Interrupt

Control

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

’C6701 Digital Signal Processor

PLL

(x1, x4)

SBSRAM

SDRAM

HOST CONNECTION

MC68360 Glueless

MPC860 Glueless

PCI9050 Bridge + Inverter

MC68302 + PAL

MPC750 + PAL

MPC960 (Jx/Rx) + PAL

† These functional units execute floating-point instructions.

TMSC6701 Datasheet(PDF) 4 Page - Texas Instruments

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