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TMSC6701 Datasheet(PDF) 1 Page - Texas Instruments |
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TMSC6701 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 64 page  TMS320C6701 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1 GFLOPS – TMS320C6201 Fixed-Point DSP Pin-Compatible D VelociTI™ Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core – Eight Highly Independent Functional Units: – Four ALUs (Floating- and Fixed-Point) – Two ALUs (Fixed-Point) – Two Multipliers (Floating- and Fixed-Point) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional D Instruction Set Features – Hardware Support for IEEE Single-Precision Instructions – Hardware Support for IEEE Double-Precision Instructions – Byte-Addressable (8-, 16-, 32-Bit Data) – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization D 1M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) D 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM – 52M-Byte Addressable External Memory Space D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI) Compatible (Motorola ™) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked-Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible D 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) D 0.18-µm/5-Level Metal Process – CMOS Technology D 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz) D 3.3-V I/Os, 1.9-V Internal (167-MHz Only) Copyright © 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 26 GJC (352-PIN BGA) PACKAGE (BOTTOM VIEW) VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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