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AR0134CS Datasheet(PDF) 15 Page - ON Semiconductor |
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AR0134CS Datasheet(HTML) 15 Page - ON Semiconductor |
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15 / 29 page  AR0134CS www.onsemi.com 15 Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued) (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C) Parameter Unit Fast-Mode Standard Mode Symbol Parameter Unit Max Min Max Min Symbol SDATA Max Load Capacitance CLOAD_SD − 30 − 30 pF SDATA Pull-up Resistor RSD 1.5 4.7 1.5 4.7 k W 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 2. Two-wire control is I2C-compatible. 3. All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXCLK = 27 MHz. 4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. I/O Timing By default, the AR0134CS launches pixel data, FV and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 15 and Table 6 for I/O timing (AC) characteristics. Figure 15. I/O Timing Diagram EXTCLK PIXCLK Data[11:0] LINE_VALID/ FRAME_VALID Pxl_0 Pxl_1 Pxl_2 Pxl_n tPFL tPLL tFP tRP tF tR 90% 90% 90% 90% 10% 10% 10% 10% tEXTCLK tPD tPLH tPFH FRAME_VALID Leads LINE_VALID by 6 PIXCLKs FRAME_VALID Trails LINE_VALID by 6 PIXCLKs Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 8) Symbol Definition Condition Min Typ Max Unit fEXTCLK Input Clock Frequency 6 − 50 MHz tEXTCLK Input Clock Period 20 − 166 ns tR Input Clock Rise Time PLL Enabled − 3 − ns tF Input Clock Fall Time PLL Enabled − 3 − ns tJITTER Input Clock Jitter − − 600 ns tcp EXTCLK to PIXCLK Propagation Delay Nominal Voltages, PLL Disabled, PIXCLK Slew Rate = 4 5.7 − 14.3 ns tRP PIXCLK Rise Time PCLK Slew Rate = 6 1.3 − 4.0 ns tFP PIXCLK Fall Time PCLK Slew Rate = 6 1.3 − 3.9 ns PIXCLK Duty Cycle 40 50 60 % fPIXCLK PIXCLK Frequency PIXCLK Slew Rate = 6, Data Slew Rate = 7 6 − 74.25 MHz tPD PIXCLK to Data Valid PIXCLK Slew Rate = 6, Data Slew Rate = 7 −2.5 − 2 ns |
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