AR0134CS

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20

Figure 16. Differential Output Voltage for Clock and Data Pairs

0 V (Diff)

Output Signal

is ‘Cp − Cn’ or

‘Dp − Dn’

Table 17. RISE AND FALL TIMES

(Measurement Conditions: HiSPi Power Supply 0.4 V, Max Freq. 700 MHz)

Symbol

Parameter

Min

Typ

Max

Unit

1/UI

Data Rate

280

–

700

Mb/s

TxPRE

Max Setup Time from Transmitter (Note 17)

0.3

–

–

UI

TxPost

Max Hold Time from Transmitter

0.3

–

–

UI

RISE

Rise Time (20% − 80%)

–

0.25 UI

–

FALL

Fall Time (20% − 80%)

150 ps

0.25 UI

–

PLL_DUTY

Clock Duty

45

50

55

%

Bitrate Period (Note 17)

1.43

−

3.57

ns

Eye Width (Notes 17, 18)

0.3

−

−

UI

Data Total Jitter (pk pk)@1e−9 (Notes 17, 18)

−

−

0.2

UI

Clock Period Jitter (RMS) (Note 18)

−

−

50

ps

Clock Cycle to Cycle Jitter (RMS) (Note 18)

−

−

100

ps

Clock to Data Skew (Notes 17, 18)

−0.1

−

0.1

UI

PHY-to-PHY Skew (Notes 17, 21)

−

−

2.1

UI

Mean Differential Skew (Note 22)

–100

−

100

ps

17. One UI is defined as the normalized mean time between one edge and the following edge of the clock.

18. Taken from 0 V crossing point.

19. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

20. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.

21. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.

22. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two