■ Harvard architecture
■ 1.25 DMIPS/MHz and 0.19 mW/MHz
■ Thumb-2 instruction set brings 32-bit performance
with 16-bit code density
■ Single cycle multiply and hardware division
■ Embedded, fast interrupt controller is now inside the
core allowing:
■ Excellent real-time behaviour
■ Low latency down to six CPU cycles inter-interrupt
■ Six CPU cycles wake-up time from low-power mode
■ Up to 35% faster and up to 45% less code than
ARM7TDMI®