DAP018x Marking, DAP018ADR2G datasheet(24/28 Pages) ONSEMI

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DAP018A/B/C/D/F

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Figure 48. A Pulldown Resistor Adjusts the Foldback Level

Foldback

Circuitry

Rload

Vfold

/ 4.2

LEB

0.8 V

10 nF

VDD

Ifold

10 m

Clock

300 mV

Skip Cycle

Comparator

Current Sense

Comparator

Reset

This point cannot

be lower than

Vfold / 4.2

Bias Reduction in Light Load

When the power supply enters deep standby mode

(skip−cycle is active), a comparator instructs the controller

that it entered in light load conditions. When this happens,

the circuit reduces various internal bias currents to further

bring its consumption down and improve the consumption

in no−load conditions.

Frequency Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. Speedking II offers a

±5% deviation

of the nominal switching frequency. The sweep sawtooth is

internally generated and modulates the clock up and down

with an adjustable period. Figure 49 displays the internal

arrangement around pin 4. It is actually a I – 2I generator,

producing a clean 50% duty−cycle sawtooth. If we take a

2 V swing on the jitter capacitor, then we calculate the

needed value for a 4 ms period, or a 250 Hz modulation

speed, again applying the V x C = I x t relationship. We need

2 ms to ramp−up and 2 ms to ramp down, therefore: C = 20

x 2 m / 2 = 20 nF. If we select a 22 nF, then our modulation

frequency will be around 227 Hz... Figure 50 shows the

relationship between the jitter ramp and the frequency

deviation.

Figure 49. An Internal Ramp is Used to Introduce

Frequency Jittering on the Oscillator Sawtooth

Frequency

Modulation

To Clock

Circuit

Ctimer

Jitter

VDD

VCjitP

VCjitV

ICjit

2.iCjit

DAP018x Marking, DAP018ADR2G Datasheet(PDF) 24 Page - ON Semiconductor

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