DSP56166ROM datasheet(26/63 Pages) MOTOROLA

26 / 63 page

PRELIMINARY - 6/15/93

MOTOROLA

DSP56166 Technical Data Sheet

2. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 20 &

21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-

triggered mode is recommended when using fast interrupt. Long interrupts are recommended

when using level-sensitive mode.

3. The interrupt instruction fetch is visible on the pins only in Mode 3.

4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover

from the STOP state. This is not the minimum required so that the IRQA interrupt is accepted.

5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting WAIT

6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the WAIT state.

7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.

Interrupt Figure 1. Asynchronous Reset Timing

Interrupt Figure 2. Synchronous Reset Timing

Interrupt Figure 3. Operating Mode Select Timing

RESET

D0-D15,

A0-A15,PS/DS

R/W,BS,PEREN

First Fetch

VIHR

CLKO

RESET

A0-A15,

PS/DS, BS,

R/W,PEREN

RESET

MODA, MODB,

MODC

VIHR

IRQA, IRQB

IRQC

VIHM

VILM

VIH

VIL

DSP56166ROM Datasheet(PDF) 26 Page - Motorola, Inc