DSP56166ROM datasheet(50/63 Pages) MOTOROLA

50 / 63 page

PRELIMINARY - 6/15/93

MOTOROLA

DSP56166 Technical Data Sheet

AC Electrical Characteristics — RSSI Timing

(VCC = 5.0 Vdc +/- 10%, TJ = -40

° to + 125° C, CL = 50 pF + 1 TTL Load, see RSSI Figure 1 and 2)

T = Icyc / 4

SCK Pin = Serial Clock

SFS Pin = Transmit/Receive Frame Sync

i ck = Internal Clock and Frame Sync

x ck = External Clock and Frame Sync

bl = bit length

wl = word length

NOTE:

All the timings for the RSSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-

inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,

all the timings remain valid by inverting the clock signal SCK and/or the frame sync SFS in the tables and

in the figures.

Num

Characteristic

60MHz

Case

Unit

Min

Max

130

SCK Clock Cycle (see Note 1)

TBD

—

i ck

131

SCK Clock High Period

TBD

—

i ck

132

SCK Clock Low Period

TBD

—

i ck

133

SCK Clock Rise/Fall Time

—

TBD

i ck

134

SCK Rising Edge to SFS In (bl)

High

—

TBD

i ck

135

SCK Rising Edge to SFS In (bl)

Low

—

TBD

i ck

136

SCK Rising Edge to SFS In

(wl) High

—

TBD

i ck

137

SCK Rising Edge to SFS In

(wl) Low

—

TBD

i ck

138

Data In Setup Time Before

SCK Falling Edge

TBD

—

i ck

139

Data In Hold Time After SCK

Falling Edge

TBD

—

i ck

DSP56166ROM Datasheet(PDF) 50 Page - Motorola, Inc

DSP56166ROM Datasheet(HTML) 50 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL