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DSP56166ROM Datasheet(PDF) 35 Page - Motorola, Inc

Part # DSP56166ROM
Description  16-bit General Purpose Digital Signal Processor
PDF  63 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56166ROM Datasheet(HTML) 35 Page - Motorola, Inc

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PRELIMINARY - 6/15/93
25
DSP56166 Technical Data Sheet
MOTOROLA
AC Electrical Characteristics
External Bus Asynchronous Timing
VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125˚ C, CL = 50 pF + 1 TTL Load.
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of Wait States, Determined by BCR Register (WS = 0 to 31)
WT = WS*cyc=2T*WS
Num
Characteristic
60MHz
Unit
Min
Max
52
WR and RD Deassertion High to BS
Assertion Low (2 Successive Bus Cycles)
TBD
TBD
ns
53
Address Valid to WR Assertion
TBD
TBD
ns
54
WR Width Assertion
WS=0
WS>0
TBD
—
—
ns
55
WR Deassertion to R/W, Address Invalid
TBD
—
ns
56
WR Assertion to D0-D15 Out Valid
TBD
TBD
ns
57
Data Out Hold Time from WR Deassertion
TBD
TBD
ns
58
Data Out Set up Time to WR
WS=0
Deassertion
WS>0
TBD
—
—
ns
59
RD Deassertion to Adress not valid
TBD
—
ns
60
Address valid to RD Deassertion
TBD
—
ns
61
Input data hold to RD Deassertion
TBD
—
ns
62
RD Assertion width
WS=0
WS>0
TBD
—
—
ns
63
Address valid to input data valid WS=0
WS>0
—
—
TBD
ns
64
Address valid to RD Assertion
TBD
ns
65
RD Assertion to input data valid WS=0
WS>0
—
—
TBD
ns
66
WR Deassertion to RD Assertion
TBD
—
ns
67
RD Deassertion to RD Assertion
TBD
—
ns
68
WR Deassertion to WR Assertion
TBD
—
ns
69
RD Deassertion toWR Assertion
TBD
—
ns



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