SLG46121V datasheet(86/98 Pages) DIALOG

86 / 98 page

000-0046121--106

Page 85 of 97

SLG46121

reg<541:539>

Internal Oscillator frequency divider control 0

000: OSC/1

001: OSC/2

010: OSC/3

011: OSC/4

100: OSC/8

101: OSC/12

110: OSC/24

111: OSC/64

reg<544:542>

Internal Oscillator frequency divider control 1

000: OSC/1

001: OSC/2

010: OSC/3

011: OSC/4

100: OSC/8

101: OSC/12

110: OSC/24

111: OSC/64

reg<545>

External Clock Source Select

0: Internal Oscillator

1: External Clock from Pin12

reg<546>

Manufacturing test mode

reg<547>

Reserved

Counter/Delay 0

reg<548>

Counter/delay0 mode selection

0: Delay Mode

1: Counter Mode

reg<551:549>

Counter/delay0 Clock Source select (external clock is

only for counter mode)

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter3 Overflow

reg<565:552>

Counter0 Control Data/Delay0 Time Control

1-16384: (delay time = (counter control data +2)

/freq)

reg<567:566>

Delay0 Mode Select or asynchronous counter reset

00: on both falling and rising edges

01: on falling edge only

10: on rising edge only

11: no delay on either falling or rising edges

Counter/Delay 1

reg<568>

Counter/delay1 mode selection

0: Delay Mode

1: Counter Mode

reg<571:569>

Counter/delay1 Clock Source select

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter0 Overflow

reg<579:572>

Counter1 Control Data/Delay1 Time Control

1-256: (delay time = (counter control data +2) /freq)

Address

Signal Function

SLG46121V Datasheet(PDF) 86 Page - Dialog Semiconductor

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