SLG46121V datasheet(20/98 Pages) DIALOG

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SLG46121

7.0 I/O Pins

The SLG46121 has a total of 9 multi-function I/O pins which can function as either a user defined Input or Output, as well as

serving as a special function (such as outputting the voltage reference). Refer to Section 2.0 Pin Description for pin definitions.

All of the 9 user defined I/O pins on the SLG46121, exept Pin 2 can serve as both digital input and digital output. Pin 2 can only

serve as a digital input pin.

The high side of the user selectable push-pull or open-drain pin output structures for each GPIO is connected to either VDD or

VDD2. This allows for the appropriate voltage level output compatible with each voltage domain. The level shifters are located in

lower power IO PADs (pins 8, 9, 10 and 12) powered from VDD2. All configuration registers of the SLG46121 are powered from

VDD, so it is possible to maintain the configuration information even after VDD2 was turned off, discharged and turned back on

again.

7.1 Input Modes

Each I/O pin can be configured as a digital input pin with/without buffered Schmitt Trigger, or can also be configured as a low

voltage digital input. Pins 3, 4, and 6 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 3, 4, 5, 6, 8, 9, 10, and 12 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors

are 10 k

, 100 k and 1 M. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O

pins, the internal resistors can be configured as either pull-up or pull-downs.

SLG46121V Datasheet(PDF) 20 Page - Dialog Semiconductor