ADAS1000BSTZ datasheet(45/80 Pages) AD

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Data Sheet

ADAS1000/ADAS1000-1/ADAS1000-2

BIVENTRICULAR PACERS

As described previously, the pace algorithm expects the pace pulse

to be less than 2 ms wide. In a pacer where both ventricles are

paced, they can be paced simultaneously. Where they fall within

the width and height limits programmed into the algorithm, a

valid pace is flagged, but only one pace pulse may be visible.

With the pace width filter enabled, the pace algorithm seeks

pace pulse widths within a 100 μs to 2 ms window. Assuming

that this filter is enabled and in a scenario where two ventricle

pacer pulses fire at slightly different times, resulting in the pulse

showing in the lead as one large, wider pulse, a valid pace is

flagged so long as the total width does not exceed 2 ms.

PACE DETECTION MEASUREMENTS

Design verification of the ADAS1000 digital pace algorithm

includes detection of a range of simulated pace signals in

addition to using the ADAS1000 and evaluation board with

one pacemaker device connected to various simulated loads

(approximately 200 Ω to over 2 kΩ) and covering the following

4 waveform corners.

•

Minimum pulse width (100 μs), minimum height (to

<300 μV)

•

Minimum pulse width (100 μs), maximum height (up to

1.0 V)

•

Maximum pulse width (2 ms), minimum height (to <300 μV)

•

Maximum pulse width (2 ms), maximum height (up to 1.0 V)

These scenarios passed with acceptable results. The use of the

ac lead-off function had no obvious impact on the recorded

pace height, width, or the ability of the pace detection algorithm

to identify a pace pulse. The pace algorithm was also evaluated

with the respiration carrier enabled; again, no differences in the

threshold or pacer detect were noted from the carrier.

While these experiments validate the pace algorithm over a

confined set of circumstances and conditions, they do not

replace end system verification of the pacer algorithm. This

can be performed in only the end system, using the system

manufacturer’s specified cables and validation data set.

EVALUATING PACE DETECTION PERFORMANCE

ECG simulators offer a convenient means of studying the perfor-

mance and ability of the ADAS1000 to capture pace signals over

the range of widths and heights defined by the various regulatory

standards. While the pace detection algorithm of the ADAS1000

is designed to conform to medical instrument standards (pace

widths of 100 μs to 2.00 ms and with amplitudes of <400 μV to

>1000 mV), some simulators put out signals wider or narrower

than called for in the standards. The pace detection algorithm

has been designed to measure a maximum pace widths of 2 ms

with a margin of 0.25 ms to allow for simulator variations.

PACE WIDTH

The ADAS1000 is capable of measuring pace widths of 100 μs

to 2.00 ms. The measured pace width is available through the

PACExDATA registers. These registers have limited resolution.

The minimum pace width is 101.56 μs and the maximum is

2.00 ms. The pace detection algorithm always returns a width

greater than what is measured at the 50% point, ensuring that

the algorithm is capable of measuring a narrow 100 μs pulse. A

valid pulse width of 100 μs is reported as 101.56 μs. Any valid

pace pulses ≥ 2.00 ms and ≤ 2.25 ms are reported as 2.00 ms.

PACE LATENCY

The pace algorithm always examines 128 kHz, 16-bit ECG data,

regardless of the selected frame rate and ECG filter setting. A

pace pulse is qualified when a valid trailing edge is detected and

is flagged in the next available frame header. Pace and ECG data

is always correctly time-aligned at the 128 kHz frame rate, but

the additional filtering inherent in the slower frame rates delays

the ECG data of the frame relative to the pace pulse flag. These

delays are summarized in Table 16 and must be taken into account

to enable correct positioning of the pace event relative to the

ECG data.

There is an inherent one-frame-period uncertainty in the exact

location of the pace trailing edge.

PACE DETECTION VIA SECONDARY SERIAL

INTERFACE (ADAS1000 AND ADAS1000-1 ONLY)

The ADAS1000/ADAS1000-1 provide a second serial interface

for users who want to implement their own pace detection

schemes. This interface is configured as a master interface. It

provides ECG data at the 128 kHz data rate only. The purpose

of this interface is to allow the user to access the ECG data at a

rate sufficient to allow them to run their own pace algorithm,

while maintaining all the filtering and decimation of the ECG

data that the ADAS1000/ADAS1000-1 offer on the standard

serial interface (2 kHz and 16 kHz data rates). This dedicated

pace interface uses three of the four GPIO pins, leaving one

GPIO pin available even when the secondary serial interface

is enabled. Note that the on-chip digital calibration to ensure

channel gain matching does not apply to data that is available

on this interface. This interface is discussed in more detail in

the Secondary Serial Interface section.

Rev. B | Page 45 of 80

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