AD9674KBCZ datasheet(33/48 Pages) AD

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AD9674

Data Sheet

Rev. A | Page 32 of 47

CW DOPPLER OPERATION

Each channel of the AD9674 includes an I/Q demodulator. Each

demodulator has an individual programmable phase shifter.

The I/Q demodulator is ideal for phased array beamforming

applications in medical ultrasound. Each channel can be

programmed for 16 phase settings/360° (or 22.5°/step), selectable

via the SPI port. The device has a RESET± input that is used to

synchronize the LO dividers of each channel. If multiple AD9674

devices are used, a common reset across the array ensures a synch-

ronized phase for all channels. Internal to the AD9674, the

individual Channel I and Channel Q outputs are current summed.

If multiple AD9674 devices are used, the I and Q outputs from

each AD9674 can be current summed and converted to a voltage

using an external transimpedance amplifier.

Quadrature Generation

The internal 0° and 90° LO phases are digitally generated by a

divide by M logic circuit, where M is 4, 8, or 16. The internal

divider is selected via Address 0x02E, Bits[2:1] (see Table 25). The

divider is dc-coupled and inherently broadband; the maximum

LO frequency is limited only by its switching speed. The duty

cycle of the quadrature LO signals must be as close to 50% as

possible for the 4LO and 8LO modes. The 16LO mode does not

require a 50% duty cycle. Furthermore, the divider is implemented

so the multiple LO signal reclocks the final flip flops that generate

the internal LO signals and, therefore, minimizes noise introduced

by the divide circuitry.

For optimum performance, the MLO± input is driven differentially,

as on the AD9670 evaluation board. The common-mode voltage

on each pin is approximately 1.2 V with the nominal 3 V supply.

It is important to ensure that the MLO± source has very low phase

noise (jitter), a fast slew rate, and an adequate input level to

obtain optimum performance of the CW signal chain.

Beamforming applications require a precise channel-to-channel

phase relationship for coherence among multiple channels. The

RESET± input is provided to synchronize the LO divider circuits in

different AD9674 devices when they are used in arrays. The

RESET± input is a synchronous edge triggered input that resets the

dividers to a known state after power is applied to multiple

AD9674 devices.

The RESET± signal can be either a continuous signal or a single

pulse, and can be either synchronized with the MLO± clock edge

(recommended) or it can be asynchronous. If a continuous signal is

used for the RESET±, it must be at the LO rate. For a

synchronous RESET±, the device can be configured to sample

the RESET± signal with either the falling or rising edge of the

MLO± clock, which makes it easier to align the RESET± signal

with the opposite MLO± clock edge. Register 0x02E is used to

configure the RESET± signal behavior. Synchronize the RESET±

input to the MLO± input. Accurate channel to channel phase

matching can be achieved via a common clock on the RESET±

input when using more than one AD9674 device.

I/Q Demodulator and Phase Shifter

The I/Q demodulators consist of double balanced, harmonic

rejection, passive mixers. The RF input signals are converted

into currents by transconductance stages that have a maximum

differential input signal capability matching the full-scale LNA

output. These currents are then presented to the mixers, which

convert them to baseband (RF − LO) and 2× RF (RF + LO).

The signals are phase shifted according to the codes that are

programmed into the SPI latch (see Table 20). The phase shift

function is an integral part of the overall circuit. The phase shift

listed in Table 20 is defined as being between the baseband I or Q

channel outputs. As an example, for a common signal applied to

a pair of RF inputs to an AD9674, the baseband outputs are in

phase for matching phase codes. However, if the phase code for

Channel 1 is 0000 and the phase code for Channel 2 is 0001,

Channel 2 leads Channel 1 by 22.5°.

Table 20. Phase Select Code for Channel to Channel Phase Shift

Φ Shift

I/Q Demodulator Phase (Address 0x02D, Bits[3:0])

0°

0000

22.5°

0001 (not valid in 4LO mode)

45°

0010

67.5°

0011 (not valid in 4LO mode)

90°

0100

112.5°

0101 (not valid in 4LO mode)

135°

0110

157.5°

0111 (not valid in 4LO mode)

180°

1000

202.5°

1001 (not valid in 4LO mode)

225°

1010

247.5°

1011 (not valid in 4LO mode)

270°

1100

292.5°

1101 (not valid in 4LO mode)

315°

1110

337.5°

1111 (not valid in 4LO mode)

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