AD9674

Data Sheet

Rev. A | Page 8 of 47

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, and

digital HPF bypassed, unless otherwise noted.

Table 3.

Temperature

Min

Typ

Max

Unit

CLOCK2

Clock Rate

40 MSPS (Mode I)

Full

20.5

40

MHz

65 MSPS (Mode II)

Full

20.5

65

MHz

Full

20.5

80

MHz

Full

20.5

125

MHz

Full

3.75

ns

Full

3.75

ns

Full

10.8

ns

Full

300

ps

Full

300

ps

Full

ns

Full

10.8

ns

Full

ns

Full

ps

Full

ps

Full

±225

±400

ps

25°C

1

ns

25°C

1

ns

Wake-Up Time (Standby)

25°C

2

µs

Wake-Up Time (Power-Down)

25°C

375

µs

ADC Pipeline Latency

Full

16

Clock cycles

APERTURE

25°C

<1

ps rms

LO GENERATION

MLO± Frequency

4LO Mode

Full

4

40

MHz

8LO Mode

Full

8

80

MHz

16LO Mode

Full

16

160

MHz

Full

1

ns

Full

1

ns

1

For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, UnderstandingHigh SpeedADCTestingandEvaluation.

2

The clock can be adjusted via the SPI.

3

Mode III must have the RF decimator enabled, unless DVDD runs at 1.8 V and 12-bit mode is configured.

4

Mode IV must have the RF decimator enabled.

5

Measurements were made using the device soldered to FR-4 material.

6

7