AD9674KBCZ datasheet(38/48 Pages) AD

38 / 48 page

Data Sheet

AD9674

Rev. A | Page 37 of 47

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

SDIO

SCLK

CSB

tDH

tHIGH

tCLK

tLOW

tDS

R/W

A12

A11

A10

Figure 54. Serial Timing Details

Table 23. Serial Timing Definitions

Parameter

Timing (ns min)

Description

tDS

12.5

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

(not shown in Figure 54)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not

shown in Figure 54)

AD9674KBCZ Datasheet(PDF) 38 Page - Analog Devices

AD9674KBCZ Datasheet(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL