Data Sheet

AD9674

Rev. A | Page 9 of 47

ADC Timing Diagram

DCO–

DCO+

DOUTx–

DOUTx+

FCO–

FCO+

AIN

CLK–

CLK+

TX_TRIG+

TX_TRIG–

MSB

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D9

N – 17

D8

N – 17

D7

N – 17

D6

N – 17

D5

N – 17

D4

N – 17

D3

N – 17

D2

N – 17

D1

N – 17

D0

N – 17

D12

N – 16

MSB

N – 16

N – 1

N

Figure 2. 14-Bit Data Serial Stream (Default, RF Decimator Bypassed, Digital HPF Bypassed), One Channel per Lane Mode, FCO Mode = Word

CW Doppler Timing Diagram

MLO–

MLO+

RESET–

RESET+

Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode

MLO–

MLO+

RESET–

RESET+

Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode