VSC8113 datasheet(14/28 Pages) VITESSE

14 / 28 page

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8113

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Page 14

G52154-0, Rev 4.2

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

3/19/99

Table 13: Clock Multiplier Unit Performance

(1)

These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements

(< 10 mUIrms)

(2)

Needed to meet SONET output frequency stability requirements

(3)

Measured

Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.

AC Characteristics

Table 14: PECL and TTL Outputs

Name

Description

Min

Typ

Max

Units

RCd

Reference clock duty cycle

RCj

Reference clock jitter (RMS) @ 77.76 MHz ref (1)

RCj

Reference clock jitter (RMS) @ 51.84 MHz ref (1)

RCj

Reference clock jitter (RMS) @ 38.88 MHz ref (1)

9ps

RCj

Reference clock jitter (RMS) @ 19.44 MHz ref (1)

5ps

RCf

Reference clock frequency tolerance (2)

-20

+20

ppm

OCj

Output clock jitter (RMS) @ 77.76 MHz ref (3)

8ps

OCj

Output clock jitter (RMS) @ 51.84 MHz ref (3)

OCj

Output clock jitter (RMS) @ 38.88 MHz ref (3)

OCj

Output clock jitter (RMS) @ 19.44 MHz ref (3)

OCfrange

Output frequency

620

624

MHz

OCd

Output clock duty cycle

Parameters

Description

Min

Typ

Max

Units

Conditions

TR,TTL

TTL Output Rise Time

—2

—

10-90%

TF,TTL

TTL Output Fall Time

—1.5

—

10-90%

TR,PECL

PECL Output Rise Time

—350

—

20-80%

TF,PECL

PECL Output Fall Time

—350

—

20-80%

VSC8113 Datasheet(PDF) 14 Page - Vitesse Semiconductor Corporation

VSC8113 Datasheet(HTML) 14 Page - Vitesse Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL