VSC8113 datasheet(15/28 Pages) VITESSE

15 / 28 page

G52154-0, Rev 4.2

Page 15

3/19/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8113

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

DC Characteristics

Table 15: PECL and TTL Inputs and Outputs

Parameters

Description

Min

Typ

Max

Units

Conditions

VOH

Output HIGH

voltage (PECL)

——

VDDP – 0.9V

—

VOL

Output LOW

voltage (PECL)

0.7

——

—

VOCM

O/P Common

Mode Range

(PECL)

1.1

—VDDP – 1.3V

—

∆V

OUT75

Differential

Output Voltage

(PECL)

600

—1300

Ω to V

DDP – 2.0 V

∆V

OUT50

Differential

Output Voltage

(PECL)

600

—1300

Ω to V

DDP – 2.0 V

VIH

Input HIGH

voltage (PECL)

VDDP – 0.9V

—

VDDP – 0.3V

For single ended

VIL

Input LOW

voltage (PECL)

0—

VDDP – 1.72V

For single ended

∆V

Differential Input

Voltage (PECL)

400

—

1600

—

VICM

I/P Common

Mode Range

(PECL)

1.5 –

∆V

IN/2

—

VDDP – 1.0 – ∆VIN/2

—

VOH

Output HIGH

voltage (TTL)

2.4

——

IOH = -1.0 mA

VOL

Output LOW

voltage (TTL)

——

0.5

IOL = +1.0 mA

VIH

Input HIGH

voltage (TTL)

2.0

—

5.5

—

VIL

Input LOW

voltage (TTL)

—0.8

—

IIH

Input HIGH

current (TTL)

—50

500

µA

2.0V< VIN < 5.5V,

Typical@2.4V

IIL

Input LOW

current (TTL)

——

-500

µA

-0.5V < VIN < 0.8V

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