VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8113

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Page 24

© VITESSE SEMICONDUCTOR CORPORATION

G52154-0, Rev 4.2

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

3/19/99

Application Notes

Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)

The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8113 has been brought off-chip to allow as

much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both

the VSC8113 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI

device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data

out for the PM5355), which utilizes most of the 12.86ns period (at 78MHz), leaving little for the trace delays

and set-up times required to interconnect the 2 devices.

The VSC8113 and the UNI device should be placed as close to each other as possible to provide maximum

setup and hold time margin at the inputs of the VSC8113. Figure 12 suggests two different ways of routing the

TXLSCKOUT-to-TXLSCKIN clock trace when used in a 622 MHz mode, which ever method is used the trans-

mission line trace impedance should be no lower than 75 ohms.

Figure 12: Interconnecting the Byte Clocks

(1) TXLSCKOUT and TXLSCKIN are tied together at the pins of the VSC8113. This provides a setup and

hold time margin for the TXIN input of

(2) TXLSCKOUT is daisy chained to the UNI device and then routed back to the VSC8113 along with the

byte data. This interface provides a setup and hold time margin for the TXIN input of

to be less than 0.43ns (~3 inches).

The general recommendation is to apply option (1) and place the VSC8113 and PM5355 as close to each

other as possible. If the one-way trace delay cannot be kept less than 0.43ns with a 50 pf load, daisy-chaining

(option 2) should be applied - close attention must be paid to signal routing in this case because of the lack of

hold time margin.

TXIN[7:0]

TXLSCKIN

TXLSCKOUT

PM5355

VSC8113

(1)

(2)

POUT[7:0]

TCLK