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HT85F2240 Datasheet(PDF) 79 Page - Holtek Semiconductor Inc |
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HT85F2240 Datasheet(HTML) 79 Page - Holtek Semiconductor Inc |
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79 / 147 page ![]() Rev. 1.10 79 of 147 ���� �1� �01� A/D Flash 8051 Core Low Pin Count MCU HT85F2230/HT85F2240 24 Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or Time Base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain multiple external interrupt pins, while the internal interrupts are generated by the various functions such as Timer/Event Counters, Time Base, LVD and the A/D converter. In addition, the interrupt priority can be controlled using registers. Interrupt Registers Overall interrupt control, which means interrupt enabling, priority and request flag setting, is controlled using several registers. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be automatically set by the microcontroller. The global enable control bit if cleared to zero will disable all interrupts. Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Function Registers, as shown in the accompanying table. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. Interrupt Register Bit Naming Conventions Function Enable Bit Request Flag Notes G�oba� EAL — — INTn Pin EXn IEn n=0~1 A/D Converter EADC IADC — Time Base ETB TBF — LVD ELVD LVDF — Timer n ETn TFn n=0~� CCUn ECCUn CCUnF n=0~1 Timer � Externa� Re�oad EXEN� EXF� — Interrupt Register Contents Register Name Bit 7 6 5 4 3 2 1 0 IEN0 EAL (WDT) ET� — ET1 EX1 ET0 EX0 IEN1 EXEN� (SWDT) — — — — ECCU1 ECCU0 IEN� — — — — — — ELVD — IEN� — — — — ETB EADC — — IRCON EXF� TF� — — CCU1F CCU0F — — IRCON� — — — — LVDF TBF — IADC TCON TF1 (TR1) TF0 (TR0) IE1 IT1 IE0 IT0 T�CON — I�FR — (T�R1) (T�R0) (T�CM) (T�I1) (T�I0) Note: The bits in brackets are �sed to manage other f�nctions and not re�ated to the interr�pt contro�. |
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