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PIC18F4539-E/MLSQTP Datasheet(PDF) 69 Page - Microchip Technology

Part # PIC18F4539-E/MLSQTP
Description  Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
PDF  322 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4539-E/MLSQTP Datasheet(HTML) 69 Page - Microchip Technology

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 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 67
PIC18FXX39
7.0
8 X 8 HARDWARE MULTIPLIER
7.1
Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX39 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
7.2
Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 7-1:
PERFORMANCE COMPARISON
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF
ARG1,
W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
ARG2,
SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG1
MOVF
ARG2,
W
BTFSC
ARG1,
SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
6.9
µs27.6 µs69 µs
Hardware multiply
1
1
100 ns
400 ns
1
µs
8 x 8 signed
Without hardware multiply
33
91
9.1
µs36.4 µs91 µs
Hardware multiply
6
6
600 ns
2.4
µs6 µs
16 x 16 unsigned
Without hardware multiply
21
242
24.2
µs96.8 µs
242
µs
Hardware multiply
28
28
2.8
µs
11.2
µs28 µs
16 x 16 signed
Without hardware multiply
52
254
25.4
µs
102.6
µs
254
µs
Hardware multiply
35
40
4.0
µs16.0 µs40 µs



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