PIC18F4539-ESLASHMLSQTP datasheet(75/322 Pages) MICROCHIP

75 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 73

PIC18FXX39

INTCON3 REGISTER

R/W-1

U-0

R/W-0

U-0

R/W-0

INT2IP(1)

INT1IP(1)

—INT2IE

INT1IE

—

INT2IF

INT1IF

bit 7

bit 0

bit 7

INT2IP(1): INT2 External Interrupt Priority bit

= High priority

= Low priority

bit 6

INT1IP(1): INT1 External Interrupt Priority bit

= High priority

= Low priority

bit 5

Unimplemented: Read as '0'

bit 4

INT2IE: INT2 External Interrupt Enable bit

= Enables the INT2 external interrupt

= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

= Enables the INT1 external interrupt

= Disables the INT1 external interrupt

bit 2

Unimplemented: Read as '0'

bit 1

INT2IF: INT2 External Interrupt Flag bit

= The INT2 external interrupt occurred (must be cleared in software)

= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

= The INT1 external interrupt occurred (must be cleared in software)

= The INT1 external interrupt did not occur

Note

1: Maintain this bit cleared (= 0).

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

PIC18F4539-E/MLSQTP Datasheet(PDF) 75 Page - Microchip Technology

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