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PIC18F4539-E/MLSQTP Datasheet(PDF) 90 Page - Microchip Technology

Part # PIC18F4539-E/MLSQTP
Description  Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
PDF  322 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4539-E/MLSQTP Datasheet(HTML) 90 Page - Microchip Technology

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PIC18FXX39
DS30485A-page 88
Preliminary
 2002 Microchip Technology Inc.
TABLE 9-3:
PORTB FUNCTIONS
TABLE 9-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit#
Buffer
Function
RB0/INT0
bit0
TTL/ST(1)
Input/output pin or external interrupt input0.
Internal software programmable weak pull-up.
RB1/INT1
bit1
TTL/ST(1)
Input/output pin or external interrupt input1.
Internal software programmable weak pull-up.
RB2/INT2
bit2
TTL/ST(1)
Input/output pin or external interrupt input2.
Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin.
Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/PGM(4)
bit5
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.
RB6/PGC
bit6
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
RB7/PGD
bit7
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Legend:
TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP
must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
RESETS
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
LATB
LATB Data Output Register
xxxx xxxx
uuuu uuuu
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—RBIP
1111 -1-1
1111 -1-1
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
11-0 0-00
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.



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