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FAN5353MPX Datasheet(PDF) 3 Page - ON Semiconductor

Part # FAN5353MPX
Description  3 MHz, 3 A Synchronous Buck Regulator
PDF  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
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FAN5353MPX Datasheet(HTML) 3 Page - ON Semiconductor

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© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5353 • Rev. 1.0.3
2
Table 1. Recommended External Components for 3 A Maximum Load Current
Component
Description
Vendor
Parameter
Typ.
Units
L1
470 nH nominal
Vishay — IHLP1616ABER47M01
Coiltronics — SD12-R47-R
TDK — VLC5020T-R47N,
MURATA — LQH55PNR47NT0
L
0.47
µH
DCR
20
m
Ω
COUT
2 pieces
10
µF, 6.3 V, X5R, 0805
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
C
10.0
µF
CIN
10
µF, 6.3 V, X5R, 0805
CIN1
10 nF, 25 V, X7R, 0402
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
C
10
nF
CVCC
4.7
µF, 6.3 V, X5R, 0603
GRM188R60J475K (Murata)
C1608X5R0J475K (TDK)
C
4.7
µF
R3
(1)
Resistor: 1
Ω 0402
any
R
1
Ω
Note:
1.
R3 is optional and improves IC power supply noise rejection. See Layout recommendations for more information.
Pin Configuration
Figure 2. 12-Pin, 3 x 3.5 mm MLP (Top View)
Pin Definitions
Pin #
Name
Description
1
FB
FB. Connect to resistor divider. The IC regulates this pin to 0.8 V.
2
VOUT
VOUT. Sense pin for VOUT. Connect to COUT.
3, 4
PGND
Power Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a
minimal path to these pins.
5, 6
SW
Switching Node. Connect to inductor.
P1
GND
Ground. All signals are referenced to this pin.
7, 8
PVIN
Power Input Voltage. Connect to input power source. Connect to CIN with minimal path.
9
VCC
IC Bias Supply. Connect to input power source. Use a separate bypass capacitor CVCC from this pin
to the P1 GND terminal between pins 1 and 12.
10
EN
Enable. The device is in shutdown mode when this pin is LOW. Do not leave this pin floating.
11
PGOOD
Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
12
NC
This pin has no function and should be tied to GND.
Note:
2.
P1 is the bottom heat-sink pad. Ground plane should flow through pins 3, 4, 12, and P1 and can be extended through pin
11 if PGOOD’s function is not required to improve IC cooling.
FB
VOUT
PGND
PGND
SW
SW
NC
PGOOD
EN
VCC
PVIN
PVIN
6
5
4
3
2
1
7
8
9
10
11
12
P1
(GND)



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