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CYUSB306X Datasheet(PDF) 23 Page - Cypress Semiconductor |
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CYUSB306X Datasheet(HTML) 23 Page - Cypress Semiconductor |
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23 / 37 page ![]() CYUSB306X Document Number: 001-87516 Rev. *L Page 23 of 37 I2S Timing Diagram Figure 9. I2S Transmit Cycle tT tTR tTF tTL tThd tTd tTH SCK SA, WS (output) Table 12. I2S Timing Parameters[3] Parameter Description Min Max Units tT I2S transmitter clock cycle tTR – ns tTL I2S transmitter cycle LOW period 0.35 tTR – ns tTH I2S transmitter cycle HIGH period 0.35 tTR – ns tTR I2S transmitter rise time – 0.15 tTR ns tTF I2S transmitter fall time – 0.15 tTR ns tThd I2S transmitter data hold time 0 – ns tTd I2S transmitter delay time – 0.8 tT ns Note tT is selectable through clock gears. Max tTR is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz). Note 3. All parameters guaranteed by design and validated through characterization. |
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