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CYUSB306X Datasheet(PDF) 26 Page - Cypress Semiconductor |
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CYUSB306X Datasheet(HTML) 26 Page - Cypress Semiconductor |
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26 / 37 page ![]() CYUSB306X Document Number: 001-87516 Rev. *L Page 26 of 37 Reset Sequence CX3’s hard reset sequence requirements are specified in this section. Figure 11. Reset Sequence Table 14. Reset and Standby Timing Parameters Parameter Definition Conditions Min (ms) Max (ms) tRPW Minimum RESET# pulse width Clock Input 1 – tRH Minimum HIGH on RESET# – 5 – tRR Reset recovery time (after which the boot loader begins firmware download) Clock Input 1 – tSBY Time to enter standby/suspend mode (from the time MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set) – – 1 tWU Time to wakeup from standby Clock Input 1 – tWH Minimum time before standby/suspend source may be reasserted – 5 – VDD (core ) xVDDQ CLKIN RESET# Mandatory Reset Pulse Hard Reset tRPW tRh Standby/ Suspend Source Standby/Suspend source Is asserted (MAIN_POWER_EN/ MAIN_CLK_EN bit is set) Standby/Suspend source Is deasserted tSBY tWU CLKIN must be stable before exiting Standby/Suspend tRR tWH |
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