P89LPC904FD datasheet(15/41 Pages) PHILIPS

Part #	P89LPC904FD

Description	8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter

PDF	41 Pages

Scroll/Zoom	100%

Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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15 / 41 page

Philips Semiconductors

P89LPC904

8-bit microcontrollers with two-clock accelerated 80C51 core

Preliminary data

Rev. 02 — 25 June 2004

15 of 41

9397 750 13521

8.6 CPU CLock (CCLK) wake-up delay

The P89LPC904 has an internal wake-up timer that delays the clock until it stabilizes

depending to the clock source used.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to

lower the power consumption further. On any reset, CLKLP is logic 0.

P89LPC904FD Datasheet(PDF) 15 Page - NXP Semiconductors