Philips Semiconductors

P89LPC904

8-bit microcontrollers with two-clock accelerated 80C51 core

Preliminary data

Rev. 02 — 25 June 2004

30 of 41

9397 750 13521

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

8.25 Watchdog timer

The Watchdog timer causes a system reset when it underflows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer

can only be reset by a power-on reset. When the Watchdog feature is disabled, it can

be used as an interval timer and may generate an interrupt. Figure 9 shows the

Watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte

sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,

the Watchdog is disabled. The Watchdog timer has a time-out period that ranges

from a few

µs to a few seconds. Please refer to the P89LPC904 User’s Manual for

more details.

8.26 Additional features

8.26.1

Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or Watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.26.2

Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that

the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing

the AUXR1 register, without the possibility of inadvertently altering other bits in the

register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 9.

Watchdog timer in Watchdog mode (WDTE = 1).

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aaa905

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

PCLK

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

reset (1)