SAFC161RI datasheet(45/60 Pages) SIEMENS

45 / 60 page

Semiconductor Group

1998-05-01

C161RI

RD to valid data in

(with RW-delay)

–

43 +

–

2TCL - 20

RD to valid data in

(no RW-delay)

–

74 +

–

3TCL - 20

ALE low to valid data in

–

A + tC

–

3TCL - 20

A + tC

Address to valid data in

–

+ 2

A + tC

–

4TCL - 30

+ 2

A + tC

Data hold after RD

rising edge

0–0

–

Data float after RD

–

49 +

–

2TCL - 14

Data valid to WR

43 +

–

2TCL - 20

–ns

Data hold after WR

49 +

–

2TCL - 14

–ns

ALE rising edge after RD,

49 +

–

2TCL - 14

–ns

Address hold after RD,

49 +

–

2TCL - 14

–ns

ALE falling edge to CS

– 4 -

10 -

– 4 -

10 -

CS low to Valid Data In

–

C + 2tA

–

3TCL - 20

C + 2tA

CS hold after RD, WR

80 +

–

3TCL - 14

–ns

ALE fall. edge to RdCS,

WrCS (with RW delay)

27 +

–TCL - 4

–ns

ALE fall. edge to RdCS,

WrCS (no RW delay)

– 4 +

–-4

–ns

Address float after RdCS,

WrCS (with RW delay)

–0–

Address float after RdCS,

WrCS (no RW delay)

–

TCL

RdCS to Valid Data In

(with RW delay)

–

39 +

–

2TCL - 24

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

SAFC161RI Datasheet(PDF) 45 Page - Siemens Semiconductor Group

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