MP8869WGL datasheet(24/41 Pages) MPS

24 / 41 page

MP8869W

– 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER

MP8869W Rev. 1.02

www.MonolithicPower.com

1/18/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

I2C INTERFACE

I2C Serial Interface Description

The I2C is a 2-wire, bidirectional, serial interface

consisting of a data line (SDA) and a clock line

(SCL). The lines are pulled to a bus voltage

externally when they are idle. When connecting

to the line, a master device generates the SCL

signal and device address and arranges the

communication

sequence.

The

MP8869W

interface is an I2C slave. The I2C interface adds

flexibility to the power supply solution. The

output voltage, transition slew rate, and other

parameters can be controlled by the I2C interface

instantaneously.

Data Validity

One clock pulse is generated for each data bit

transferred. The data on the SDA line must be

stable during the high period of the clock. The

high or low state of the data line can only change

when the clock signal on the SCL line is low (see

Figure 8).

Figure 8: Bit Transfer on the I2C Bus

Start and stop are signaled by the master device,

which signifies the beginning and the end of the

I2C transfer. The start condition is defined as the

SDA signal transitioning from high to low while

the SCL is HIGH. The stop condition is defined

as the SDA signal transitioning from low to high

while the SCL is high (see Figure 9).

Figure 9: Start and Stop Conditions

Start and stop conditions are always generated

by the master. The bus is considered to be busy

after the start condition, and is considered to be

free again after a minimum of 4.7μs after the stop

condition. The bus remains busy if a repeated

start (Sr) is generated instead of a stop condition.

The start (S) and repeated start (Sr) conditions

are functionally identical.

Transfer Data

Every byte put on the SDA line must be eight bits

long. Each byte has to be followed by an

acknowledge

bit.

The

acknowledge-related

clock pulse is generated by the master. The

transmitter releases the SDA line (high) during

the acknowledge clock pulse. The receiver must

pull down the SDA line during the acknowledge

clock pulse so that it remains stable low during

the high period of this clock pulse.

Data transfers follow the format shown in Figure

10. After the start condition (S), a slave address

is sent. This address is 7 bits long followed by an

eighth bit data direction bit (R/W). A zero

indicates a transmission (write), and a one

indicates a request for data (read). A data

transfer is always terminated by a stop condition

(P) generated by the master. However, if a

master still wishes to communicate on the bus, it

can generate a repeated start condition (Sr) and

address another slave without first generating a

stop condition.

Figure 10: Complete Data Transfer

The MP8869W requires a start condition, a valid

I2C address, a register address byte, and a data

byte for a single data update. After receiving

each byte, the MP8869W acknowledges by

pulling the SDA line low during the high period of

a single clock pulse. A valid I2C address selects

the MP8869W. The MP8869W performs an

update on the falling edge of the LSB byte.

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