ISL6334DIRZ datasheet(18/28 Pages) RENESAS

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ISL6334D

FN6802 Rev 4.00

Page 18 of 28

Apr 29, 2016

Assuming the microprocessor controls the VID change at 1-bit

every tVID, the relationship between the time constant of RREF

and CREF network and tVID is given by Equation 10.

During dynamic VID transition and VID step-up, the overcurrent

trip point increases by 140% to avoid falsely triggering OCP

circuits, while the overvoltage trip point is set to its maximum VID

OVP trip level. If the dynamic VID occurs at PSI# asserted, the

system should exit PSI# and complete the transition, and then

resume PSI# operation 50µs after the transition.

Operation Initialization

Prior to converter initialization, proper conditions must exist on

the enable inputs and VCC. When the conditions are met, the

controller begins soft-start. Once the output voltage is within the

proper window of operation, VR_RDY asserts logic high.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL6334D is

released from shutdown mode.

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this threshold is

reached, proper operation of all aspects of the ISL6334D are

guaranteed. Hysteresis between the rising and falling

thresholds assure that once enabled, ISL6334D will not

inadvertently turn off unless the bias voltage drops

substantially (see “Electrical Specifications” table beginning

on page 7).

2. The ISL6334D features an enable input (EN_PWR) for power

sequencing between the controller bias voltage and another

voltage rail. The enable comparator holds the ISL6334D in

shutdown until the voltage at EN_PWR rises above 0.870V.

The enable comparator has about 130mV of hysteresis to

prevent bounce. It is important that the driver reaches its POR

level before the ISL6334D becomes enabled. The schematic

in Figure 11 demonstrates sequencing the ISL6334D with the

ISL66xx family of Intersil MOSFET drivers, which require 12V

bias.

3. The voltage on EN_VTT must be higher than 0.870V to enable

the controller. This pin is typically connected to the output of

VTT VR.

When all conditions previously mentioned are satisfied, ISL6334D

begins the soft-start and ramps the output voltage to 1.1V first.

After remaining at 1.1V for some time, ISL6334D reads the VID

code at VID input pins. If the VID code is valid, ISL6334D will

regulate the output to the final VID setting. If the VID code is OFF

code, ISL6334D will shut down, and cycling VCC, EN_PWR or

EN_VTT is needed to restart.

Soft-Start

ISL6334D based VR has 4 periods during soft-start, as shown in

Figure 12 on page 19. After VCC, EN_VTT and EN_PWR reach their

POR/enable thresholds, the controller will have a fixed delay period

tD1. After this delay period, the VR will begin first soft-start ramp

until the output voltage reaches 1.1V VBOOT voltage. Then, the

controller will regulate the VR voltage at 1.1V for another fixed

period, tD3. At the end of tD3 period, ISL6334D reads the VID

signals. If the VID code is valid, ISL6334D will initiate the second

soft-start ramp until the voltage reaches the VID voltage minus

offset voltage.

The soft-start time is the sum of the 4 periods, as shown in

Equation 11.

tD1 is a fixed delay with the typical value as 1.36ms. tD3 is

determined by the fixed 85µs plus the time to obtain a valid VID

voltage. If the VID is valid before the output reaches the 1.1V, the

minimum time to validate the VID input is 500ns. Therefore, the

minimum tD3 is about 86µs.

During tD2 and tD4, ISL6334D digitally controls the DAC voltage

change at 6.25mV per step. The time for each step is determined

by the frequency of the soft-start oscillator, which is defined by

the resistor RSS from SS pin to GND. The second soft-start ramp

time tD2 and tD4 can be calculated based on Equations 12 and

13:

CREF RREF

tVID

(EQ. 10)

FIGURE 11. POWER SEQUENCING USING THRESHOLD SENSITIVE

ENABLE (EN) FUNCTION

0.870V

EXTERNAL CIRCUIT

ISL6334D INTERNAL CIRCUIT

EN_PWR

+12V

POR

CIRCUIT

100k



9.1k



ENABLE

COMPARATOR

SOFT-START

AND

FAULT LOGIC

EN_VTT

VCC

0.870V

tSS

tD1 tD2 tD3 tD4

(EQ. 11)

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