ISL6566ACR datasheet(10/29 Pages) RENESAS

10 / 29 page

ISL6566A

FN9200 Rev 2.00

Page 10 of 29

Jul 27, 2005

VCOMP voltage crosses the sawtooth ramp, the PWM output

transitions high. The internal or external MOSFET driver

detects the change in state of the PWM signal and turns off

the synchronous MOSFET and turns on the upper MOSFET.

The PWM signal will remain high until the pulse termination

signal marks the beginning of the next cycle by triggering the

PWM signal low.

Channel-Current Balance

One important benefit of multi-phase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

In order to realize the thermal advantage, it is important that

each channel in a multi-phase converter be controlled to

carry about the same amount of current at any load level. To

achieve this, the currents through each channel must be

sampled every switching cycle. The sampled currents, In,

from each active channel are summed together and divided

by the number of active channels. The resulting cycle

average current, IAVG, provides a measure of the total load-

current demand on the converter during each switching

cycle. Channel-current balance is achieved by comparing

the sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current-

balance method is illustrated in Figure 3, with error

correction for channel 1 represented. In the figure, the cycle

average current, IAVG, is compared with the channel 1

sample, I1, to create an error signal IER.

The filtered error signal modifies the pulse width

commanded by VCOMP to correct any unbalance and force

IER toward zero. The same method for error signal

correction is applied to each active channel.

Current Sampling

In order to realize proper current-balance, the currents in

each channel must be sampled every switching cycle. This

sampling occurs during the forced off-time, following a PWM

transition low. During this time the current-sense amplifier

uses the ISEN inputs to reproduce a signal proportional to

the inductor current, IL. This sensed current, ISEN, is simply

a scaled version of the inductor current. The sample window

opens exactly 1/6 of the switching period, tSW, after the

PWM transitions low. The sample window then stays open

the rest of the switching cycle until PWM transitions high

again, as illustrated in Figure 4.

The sampled current, at the end of the tSAMPLE, is

proportional to the inductor current and is held until the next

switching period sample. The sampled current is used only

for channel-current balance.

The ISL6566A supports MOSFET rDS(ON) current sensing

to sample each channel’s current for channel-current

balance. The internal circuitry, shown in Figure 5 represents

channel n of an N-channel converter. This circuitry is

repeated for each channel in the converter, but may not be

active depending on the status of the PVCC3 and PVCC2

pins, as described in the PWM Operation section.

FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

N

IAVG



f(s)

PWM1

VCOMP

SAWTOOTH SIGNAL

IER

NOTE: Channel 2 and 3 are optional.

FILTER

TO GATE

CONTROL

LOGIC

FIGURE 4. SAMPLE AND HOLD TIMING

TIME

PWM

ISEN

SWITCHING PERIOD

SAMPLING PERIOD

OLD SAMPLE

CURRENT

NEW SAMPLE

CURRENT

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