EL4093

FN7159 Rev 0.00

Page 10 of 12

January 1996

however that this is the small signal GBWP. As mentioned

earlier, the sample and hold has special boost circuits built in

which provides ±8.5mA of charge current during full slew.

These boost circuits turn on when the S/H input differential

voltage exceeds ±50mV. When the boosters are turned on,

gm1 greatly increases and the circuit becomes nonlinear. Thus

some stability issues are associated with the boosters, and

they will be addressed in a later section.

Charge Injection and Hold Step

Charge injection refers to the charge transferred to the hold

capacitor when switching to the HOLD mode. The charge

should ideally be 0, but due to stray capacitive coupling and

other effects, is typically 0.1pC in the EL4093. This charge

changes the hold capacitor voltage by

this

V is multiplied by the output stage transconductance

(gm2) to produce a change in S/H output current. This last

quantity is listed as the spec

the following:

value of 100nA. This change in S/H output current flows

0.08mV of change at the CFA output.

Droop Rate

When the S/H amplifier is in HOLD mode, there is a small

current that leaks from the switch into the hold capacitor. This

quantity is termed the droop current, and is typically 10nA in

the EL4093. This droop current produces a ramp in the hold

capacitor voltage, which in turn produces a similar effect at the

CFA output. The Droop Rate at the CFA output can be found

using the equation below:

output due to droop current is about 7µV/µs. Recall that in

NTSC applications, there is about 60µs between autozero

periods. Thus there is 7µV/µs(60µs) = 0.4mV, or less than 0.1

IRE, of drift over each NTSC scan line. This drift is negligible in

most applications.

Choice of Hold Capacitor

The EL4093 has been designed to work with a hold capacitor

step are negligibly small for most applications. In addition, with

the special boost circuits inside the S/H, fast acquisition is

possible even using a hold capacitor of this size. Figure 5

shows the input and output of the DC-restored amplifier while

the S/H is in sample mode. Applying a +1V step to the non-

inverting input of the CFA, the output of the CFA jumps to +2V.

The S/H, however, then tries to autozero the system by driving

the CFA output back to the reference voltage. Since the input

differential across the S/H is initially +2V, the boost circuits turn

on and supply 8.5mA of charge current to the hold capacitor.

The boost circuit remains on until the CFA output has come to

within 50mV of the reference. Note that this event took only

320ns; settling to within 1% of the final value takes another

2µs. Thus for a 1V input step, acquisition takes only one to two

NTSC scan lines.

FIGURE 4.

Q

--------------------



 gm2



=

Droop

----------------------





=