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EL4093CS Datasheet(PDF) 11 Page - Renesas Technology Corp |
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EL4093CS Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 12 page ![]() EL4093 FN7159 Rev 0.00 Page 11 of 12 January 1996 A natural question arises as to whether there are other CHOLD values that can be used. In one direction, increasing CHOLD will further reduce the droop and hold step, but lengthen the acquisition time. Since the droop and hold step are already small to begin with, there is no apparent advantage to increasing CHOLD. In the other direction, decreasing CHOLD would increase the droop and hold step but shorten the acquisition time. There is, however, a caveat to reducing CHOLD: too small a CHOLD would cause the autozero loop to oscillate. The reason is that when the S/H boost circuit turns on, the input stage gm increases drastically and the circuit becomes nonlinear. A sufficiently large CHOLD must be used to suppress the non- linearity and force the loop to settle. For example, it has been found that a CHOLD of 470pF results in 1VP-P oscillation around 10MHz at the CFA output. The minimum recommended value for CHOLD is 2.2nF. With this value the loop remains stable over the entire operating temperature range (-40°C to +85°C). The greatest instability occurs at low temperatures, where we observe from the performance curves that the S/H gm’s, and hence the GBWP, are at their maximum. If the operating range is restricted to room temperature or above, then 1.5nF is sufficient to keep the loop stable. At this value of CHOLD the acquisition time reduces to about 1.5µs. Video Performance and Application Although the EL4093 is intended for high speed video applications such as SVGA, it also offers excellent performance for NTSC, with 0.04% dG and 0.02° dP at 3.58MHz. Some application considerations, however, are required for handling NTSC signals. Referring back to Figure 2, recall that typically, the autozero interval lies in the back porch portion of video containing the colorburst pulse. When the S/H compares the video to the reference voltage during this period, the colorburst (40 IREP-P) triggers the S/H boost circuit and prevents the autozero loop from settling. A remedy for this situation is to attenuate the colorburst before applying it to the S/H input. Figure 6 below shows a 3.58MHz chroma trap which would notch out the colorburst while preserving the video DC level. One may be tempted to use a RC lowpass filter to suppress the colorburst, as shown in Figure 7 below. This technique, however, poses several problems. First, to obtain enough attenuation, we need to set the pole frequency 10 to 20 times lower than 3.58MHz. This pole, being close to the auto zero loop pole, would destabilize the system and cause the loop to oscillate. Although we can cancel this pole by introducing a zero, the RC network introduces a time delay between the CFA output and the S/H input. This has undesirable effects in some NTSC applications, as Figure 8 illustrates. There is only 0.6µs from the rising edge of sync to the colorburst. If we are autozeroing over the back porch, the autozero period would begin somewhere in this 0.6µs interval. Since the edge of sync is now delayed by the RC network, autozero begins before the video back porch reaches its final value. Consequently, the autozero loop performs a correction on every line and never settles. FIGURE 5. AUTOZERO MECHANISM RESTORES AMPLIFIER OUTPUT TO GROUND AFTER +1V STEP AT INPUT FIGURE 6. COLORBURST TRAP FOR NTSC APPLICATIONS FIGURE 7. CAUTION: LOWPASS FILTER DOES NOT WORK IN NTSC APPLICATIONS |
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