IMX6SLLCEC datasheet(4/90 Pages) NXP

4 / 90 page

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

Introduction

— Cortex-A9 NEON MPE (Media Processing Engine) co-processor

The Arm Cortex-A9 includes:

•

General Interrupt Controller (GIC) with 128 interrupt support

•

Global Timer

•

256 KB unified I/D L2 cache

•

Two Master AXI (64-bit) bus interfaces output of L2 cache

•

Frequency of the core (including NEON and L1 cache) as per Table 9, "Operating Ranges," on

page 19

•

NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

•

External memory interfaces:

— 32-bit LPDDR2/LPDDR3

Each i.MX 6SLL processor enables the following interfaces to external devices (some of them are muxed

and not available simultaneously):

•

Display:

— EPDC, color, and monochrome E-INK, up to 2332x1650 resolution and 5-bit grayscale

— 24-bit parallel LCD

•

Expansion cards:

— Three MMC/SD/SDIO card ports all supporting:

– SD 3.0 support

– eMMC 5.0 support in HS400 mode

•USB:

— Two High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY

•

Miscellaneous IPs and interfaces:

— SSI block—capable of supporting audio sample frequencies up to 192 kHz stereo inputs and

outputs with I2S mode

— Five UARTs, up to 5.0 Mbps each:

– Providing RS232 interface

– Supporting 9-bit RS485 multidrop mode

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