IMX6SLLCEC datasheet(13/90 Pages) NXP

13 / 90 page

Modules List

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

3.2

Recommended Connections for Unused Analog Interfaces

Table 5 shows the recommended connections for unused analog interfaces.

RTC_XTALI/

RTC_XTALO

If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal

(

100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. Keep in mind

the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit

the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip

parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to

limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M

). This will

debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO

should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must remain

unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed

VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions.

In the case when a high accuracy real time clock is not required, the system may use an internal low

frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO

unconnected.

TEST_MODE

TEST_MODE is for NXP factory use. This signal is internally connected to an on-chip pull-down device.

The user must either disconnect this signal or tie it to GND.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO. level and the frequency should be

<32 MHz under typical conditions.

The crystal must be rated for a maximum drive level of 250

W. An ESR (equivalent series resistance) of

typically 80

 is recommended. NXP BSP (board support package) software requires 24 MHz on

XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this case,

XTALI must be directly driven by the external oscillator and XTALO is not connected. The XTALI signal

level must swing from ~0.8 x NVCC_PLL to ~0.2 V.

This clock is used as a reference for USB, so there are strict frequency tolerance and jitter requirements.

See the XTALOSC chapter and relevant interface specifications chapters of the i.MX 6SLL Reference

Manual for details.

ZQPAD

DRAM calibration resistor 240

 1% used as reference during DRAM output buffer driver calibration

should be connected between this pad and GND.

Table 4. JTAG Controller Interface Summary

JTAG

I/O Type

On-Chip Termination

JTAG_TCK

Input

47 k



pull-up

JTAG_TMS

Input

47 k



pull-up

JTAG_TDI

Input

47 k



pull-up

JTAG_TDO

3-state output

Keeper

JTAG_TRST_B

Input

47 k



pull-up

JTAG_MODE

Input

100 k



pull-up

Table 3. Special Signal Considerations (continued)

Signal Name

Remarks

IMX6SLLCEC Datasheet(PDF) 13 Page - NXP Semiconductors

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