IMX6SLLCEC datasheet(60/90 Pages) NXP

60 / 90 page

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TXC/RXC = 0) and a non-inverted frame sync (TXFS/RXFS

= 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the clock signal

TXC/RXC and/or the frame sync TXFS/RXFS shown in the tables and

in the figures.

•

All timings are on AUDMUX Pads when SSI is used for data transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of TXD (for example, during AC97 mode of operation).

4.10.10.4 SSI Receiver Timing with External Clock

Figure 34 depicts the SSI receiver external clock timing and Table 53 lists the timing parameters for the

receiver timing with the external clock.

Figure 34. SSI Receiver External Clock Timing Diagram

Table 53. SSI Receiver Timing with External Clock

Parameter

Min

Max

Unit

External Clock Operation

SS22

AUDx_TXC/AUDx_RXC clock period

81.4

—

SS23

AUDx_TXC/AUDx_RXC clock high period

—

SS24

AUDx_TXC/AUDx_RXC clock rise time

—

6.0

SS25

AUDx_TXC/AUDx_RXC clock low period

—

SS26

AUDx_TXC/AUDx_RXC clock fall time

—

6.0

SS28

AUDx_RXC high to AUDx_TXFS (bl) high

–10

15.0

SS30

AUDx_RXC high to AUDx_TXFS (bl) low

—

SS24

SS34

SS35

SS30

SS28

SS26

SS25

SS23

SS40

SS22

SS32

SS36

SS41

AUDx_TXC

(Input)

AUDx_TXFS (bl)

(Input)

AUDx_TXFS (wl)

(Input)

AUDx_RXD

(Input)

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