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AD8364ACPZ-R2 Datasheet(PDF) 20 Page - Analog Devices

Part # AD8364ACPZ-R2
Description  LF to 2.7 GHz Dual 60 dB TruPwr Detector
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8364ACPZ-R2 Datasheet(HTML) 20 Page - Analog Devices

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AD8364
Data Sheet
Rev. C | Page 20 of 44
TEMPERATURE SENSOR INTERFACE
The AD8364 provides a temperature sensor output capable of
driving about 1.6 mA. A 330 Ω-equivalent internal resistance is
connected from TEMP to COMR to provide current sink
capability. The temperature scaling factor of the output voltage is
approximately 2 mV/°C. The typical absolute voltage at 25°C is
about 620 mV.
TEMP
VPSR
INTERNAL
VPTAT
4k
1k
COMR
350
Figure 53. TEMP Interface Simplified Schematic
VREF INTERFACE
An internal voltage reference is provided to the user at Pin VREF.
The VREF voltage is a temperature stable 2.5 V reference that
can drive about 18 mA. An 830 Ω equivalent internal resistance
is connected from VREF to ACOM for 3 mA sink capability.
VREF
VPSR
INTERNAL
VOLTAGE
9k
1.465k
COMR
900
Figure 54. VREF Interface Simplified Schematic
POWER-DOWN INTERFACE
The operating and stand-by currents for the AD8364 at 25°C are
approximately 70 mA and 500 µA, respectively. The PWDN pin
is connected to an internal resistor divider made with two 42 kΩ
resistors. The divider voltage is applied to the base of an NPN
transistor to force a power-down condition when the device is
active. Typically when PWDN is pulled greater than 2 V, the
device is powered down. Figure 46 and Figure 47 show typical
response times for various RF input levels. The output reaches
to within 0.1 dB of the steady-state value in about 1.6 µs; the
reference voltage is available to full accuracy in a much shorter
time. This wake-up response vary depending on the input
coupling means and the capacitances CDEC[A, B], CHP[A, B],
and CLP[A, B].
PWDN
42k
42k
COMR
POWER DOWN
SIGNAL
Figure 55. PWDN Interface Simplified Schematic
VST[A, B] INTERFACE
The VST[A, B] interface has a high input impedance of 72 kΩ.
The voltage at VST[A, B] is converted to an internal current
used to steer the VGA gain. The VGA attenuation control is
set to 20 dB/V.
GAIN ADJUST
1.35
µA/dB
VST[A, B]
18.5k
ACOM
36k
36k
Figure 56. VST[A, B] Interface Simplified Schematic



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