P89LPC912FDH datasheet(39/63 Pages) PHILIPS

39 / 63 page

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 — 17 December 2004

39 of 63

9397 750 14468

9.17.7

Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device.

9.17.8

Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ﬁrst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = ‘0’).

9.17.9

Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

9.17.10

The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

9.18 Serial Peripheral Interface (SPI)

P89LPC912/913/914 provides another high-speed serial communication

interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous

communication bus with two operation modes: Master mode and Slave mode. Up to

4.5 Mbit/s can be supported in Master or 3 Mbit/s in Slave mode. It has a Transfer

Completion Flag and Write Collision Flag Protection.

P89LPC912FDH Datasheet(PDF) 39 Page - NXP Semiconductors