P89LPC912FDH datasheet(29/63 Pages) PHILIPS

29 / 63 page

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 — 17 December 2004

29 of 63

9397 750 14468

9.6 CPU Clock (CCLK) wake-up delay

The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it

stabilizes, depending to the clock source used. If the clock source is any of the three

crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus

60 to 100

µs. If the clock source is either the internal RC oscillator, Watchdog

oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100

µs.

9.7 CPU Clock (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

9.8 Low power select

The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.

However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’

to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz

or slower.

9.9 Memory organization

The various P89LPC912/913/914 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area.

Fig 12. Block diagram of oscillator control (P89LPC914).

002aaa483

RTC

CPU

WDT

SPI

DIVM

CCLK

OSCCLK

PCLK

TIMER 0 and

TIMER 1

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

Oscillator

clock

CPU

clock

Peripheral clock

UART

BAUD RATE

GENERATOR

CCLK

¸2

P89LPC912FDH Datasheet(PDF) 29 Page - NXP Semiconductors

P89LPC912FDH Datasheet(HTML) 29 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL