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AT77C104B Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT77C104B Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 36 page ![]() 25 AT77C104B 5347B–BIOM–08/04 Figure 14. Fast SPI Communication Communication Speed The acquisition speed of the pixels is linked to the clock’s communication speed. The faster the communication clock, the faster the authorized maximum finger sweeping speed. The sensor supports fast communications up to 16 Mbps. Reading of Frame A frame consists of 232 true columns and 1 dummy column of 8 pixels of 4 bits each. A frame starts with a dummy column. Figure 15. Example of a Frame The first dummy column, at the beginning of the pixel array, is added to the sensor to act as a specific easy-to-detect pattern, and represents the start of the frame tag. The pixel array is always read in the following order: the first byte, following the 4 bytes of the dummy column, which contains the value of the pixels physically located on the upper left corner of the array, when looking at the die with bond pads to the right. Then another 4 bytes are read that contain the value of the pixels located in the same column from top to bottom. The next column on the right is output, and so on, until the last line on the right, close to the bond pads, is output. Even values are first sent during the data serialization for SPI transfer. Therefore, the synchronization sequence on the chip’s MISO output is F0F00200. Bit2 Bit3 MSB Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 MSB SCK (Pixel Clock) MISO Transmission Clock Edge (Sensor) Reception Clock Edge (Host) Pixel 2i Pixel 2i - 1 Pixel 2i + 2 Pixel 2i + 1 p1 p2 p3 p4 p5 p6 p7 p8 0 F 0 F 2 0 0 0 Pixel Frame P9 p10 p11 P12 P13 P14 P15 p16 Synchro = F0F00200 Dummy Column 232 x 8 Pixels Column |
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